An in-depth-examination: comparative analysis of multiplication hardware accelerator algorithms in VHDL for 8-Bit Systems (WTM),(PBM) and (BWM) synthesized on an ALTERA-CYCLONE-II-DE1-Board

Andrés Gonzalo Hernández Ortega; Braian Stiven Avella Rivera; Oscar Fernando Vera; Jorge Orlando Bareño Quintero

doi:10.16925/2357-6014.2024.02.10

An in-depth-examination : comparative analysis of multiplication hardware accelerator algorithms in VHDL for 8-Bit Systems (WTM),(PBM) and (BWM) synthesized on an ALTERA-CYCLONE-II-DE1-Board

Investigación

https://doi.org/10.16925/2357-6014.2024.02.10

Andrés Gonzalo Hernández Ortega Ver Biografía

Universidad Pedagogica y Tecnologica de Colombia UPTC

Braian Stiven Avella Rivera Ver Biografía

Universidad Pedagogica y Tecnologica de Colombia UPTC

Oscar Fernando Vera Ver Biografía

Universidad Pedagogica y Tecnologica de Colombia UPTC

Jorge Orlando Bareño Quintero Ver Biografía

Universidad nacional abierta y a Distancia UNAD

This article presents an implementation and comparative analysis of 8-bit Wallace Tree Multiplier (WTM), Parallel Booth Multiplier (PBM), and Baugh-Wooley Multiplier (BWM) algorithms. Introduction: this article results from research conducted for a Master’s degree in Engineering at the Pedagogical and Technological University of Colombia (UPTC) between 2022 and 2024. It analyzes and compares the performance of three multiplication algorithms (WTM, PBM, and BWM), focusing on variables such as operation time and the number of logical elements used. Problem: computing has advanced rapidly, enabling multiple operations on a single chip. This has increased the demand for components that execute tasks quickly while occupying minimal space. Multipliers are crucial in applications such as filters, DSP circuits, and fast Fourier transforms. Objective: to analyze and compare the performance of three multiplication algorithms—WTM, PBM, and BWM—tailored for 8-bit systems. Methodology: the research methodology was designed to ensure robustness and reliability. It began with formulating objectives and identifying key variables. Articles were selected based on their contributions to understanding multiplication algorithms and programming languages. The research included designing and comparing 8-bit multiplier algorithms (WTM, PBM, and BWM). Results: an analysis of the results identified the variables that contributed to significant performance improvements for each algorithm. Conclusions: the project successfully improved the efficiency of the algorithms by utilizing various register shifts and multipliers based on the operational case that benefited them the most. It achieved improvements in both efficiency and operation time concerning the use of logical elements. Originality: this research formulates strategies for applying and comparing multiplication algorithms, differentiating data processing based on specific data characteristics. Limitations: • The lack of testing systems for the implementations. • The study focused on comparing three multiplication algorithms, limiting generalizability. • Performance metrics.

Keywords: Multipliers, VHDL, ModelSim, FPGA, Full Adders, Half Adders

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[1]

A. G. Hernández Ortega, B. S. Avella Rivera, O. F. Vera, and J. O. Bareño Quintero, “An in-depth-examination: comparative analysis of multiplication hardware accelerator algorithms in VHDL for 8-Bit Systems (WTM),(PBM) and (BWM) synthesized on an ALTERA-CYCLONE-II-DE1-Board”, ing. Solidar, vol. 20, no. 2, pp. 1–29, May 2024, doi: 10.16925/2357-6014.2024.02.10.

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Vol. 20 No. 2 (2024)

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2024-05-07

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