An in-depth-examination
comparative analysis of multiplication hardware accelerator algorithms in VHDL for 8-Bit Systems (WTM),(PBM) and (BWM) synthesized on an ALTERA-CYCLONE-II-DE1-Board
This article presents an implementation and comparative analysis of 8-bit Wallace Tree Multiplier (WTM), Parallel Booth Multiplier (PBM), and Baugh-Wooley Multiplier (BWM) algorithms. Introduction: this article results from research conducted for a Master’s degree in Engineering at the Pedagogical and Technological University of Colombia (UPTC) between 2022 and 2024. It analyzes and compares the performance of three multiplication algorithms (WTM, PBM, and BWM), focusing on variables such as operation time and the number of logical elements used. Problem: computing has advanced rapidly, enabling multiple operations on a single chip. This has increased the demand for components that execute tasks quickly while occupying minimal space. Multipliers are crucial in applications such as filters, DSP circuits, and fast Fourier transforms. Objective: to analyze and compare the performance of three multiplication algorithms—WTM, PBM, and BWM—tailored for 8-bit systems. Methodology: the research methodology was designed to ensure robustness and reliability. It began with formulating objectives and identifying key variables. Articles were selected based on their contributions to understanding multiplication algorithms and programming languages. The research included designing and comparing 8-bit multiplier algorithms (WTM, PBM, and BWM). Results: an analysis of the results identified the variables that contributed to significant performance improvements for each algorithm. Conclusions: the project successfully improved the efficiency of the algorithms by utilizing various register shifts and multipliers based on the operational case that benefited them the most. It achieved improvements in both efficiency and operation time concerning the use of logical elements. Originality: this research formulates strategies for applying and comparing multiplication algorithms, differentiating data processing based on specific data characteristics. Limitations: • The lack of testing systems for the implementations. • The study focused on comparing three multiplication algorithms, limiting generalizability. • Performance metrics.
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[1] S. Karunamurthi and K. Vijeyakumar, “A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme,” Circuits, Systems, and Signal Processing, vol. 40, pp. 3-6, 2021, doi: 10.1007/s00034-020-01549-w.
[2] S. Núñez Mejía, “Hidden Markov Models for early detection of cardiovascular diseases,” Ing. Solidar., vol. 20, no. 1, pp. 1–31, Dec. 2023, doi: 10.16925/2357-6014.2024.01.02.
[3] E. J. Rao, T. Ramanjaneyulu, and K. J. Kumar, “Advanced multiplier design and implementation using Hancarlson adder,” pp. 1-6, 2018, doi: 10.1109/ICONIC.2018.8601252.
[4] Y. Chang et al., “A Low Power Radix-4 Booth Multiplier with Pre-Encoded Mechanism,” IEEE Access, pp. 1-2, 2020, doi: 10.1109/ACCESS.2020.3003684.
[5] K. Saritha Raj et al., “Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates,” International Review of Applied Sciences and Engineering, vol. 14, no. 2, pp. 285-292, 2023, doi: 10.1556/1848.2022.00550.
[6] D. Gokulakrishan, R. Ramakrishnan, G. Saritha, and B. Sreedevi, “An advancing method for web service reliability and scalability using ResNet convolution neural network optimized with Zebra Optimization Algorithm,” Trans. Emerging Tel. Tech., vol. 35, no. 5, pp. 2-8, 2024, doi: 10.1002/ett.4968.
[7] N. Behera, M. Pradhan, and P. Mishro, “Analysis of Combinational Delay in Signed Binary Multiplier,” in 2022 International Conference on Connected Systems & Intelligence (CSI), 2022, pp. 1-4, doi: 10.1109/CSI54720.2022.9924000.
[8] T. A. Rather et al., “Modelling and simulation of a reversible quantum logic based 4x3 multiplier design for nanotechnology applications,” Int. J. Theor. Phys., vol. 59, no. 1, pp. 57–67, 2020, doi: 10.1007/s10773-019-04285-3.
[9] V. Pala, V. Makhe, K. Bhuva, and R. Parekh, “RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier,” in 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO), 2022, pp. 1-6, doi: 10.1109/5nano53044.2022.9828876.
[10] C. K., D., V., and M. I., “Design of Power Delay Efficient Wallace Multiplier,” in 2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS), 2023, pp. 972-976, doi: 10.1109/ICACCS57279.2023.10112916.
[11] A. Jain, S. Bansal, S. Khan, S. Akhter, and S. Chaturvedi, “Implementation of an Efficient N×N Multiplier Based on Vedic Mathematics and Booth-Wallace Tree Multiplier,” in 2019 International Conference on Power Electronics, Control and Automation (ICPECA), 2019, pp. 1-5, doi: 10.1109/ICPECA47973.2019.8975673.
[12] M. García-Parra, N. Plazas-Leguizamón, R. Colmenares-Cruz, N. Moreno-López, and A. Barrera-Siabato, “Technological surveillance of energy efficiency in agricultural production systems: a systematic review,” Portal SOAR: Sapienza Open Access Repository, vol. 7, pp. 67-78, 2024, doi: 10.56183/soar.v7iEBOA7.39.
[13] Thamizharasan Viswanathan and P. Pavithra, “Design and analysis of Wallace tree multiplier using approximate full adder and kogge stone adder,” Ijireeice, 2023, doi: 10.17148/IJIREEICE.2023.11303.
[14] A. Mokhtar, N. Zahari, C. Ping, M. Mustapha, N. Ismail, and S. Ismail, “Implementation of Modified Booth-Wallace Tree Multiplier in FPGA,” Journal of Computer Science & Computational Mathematics, vol. 11, pp. 49-52, 2021, doi: 10.20967/jcscm.2021.03.003.
[15] B. Mukherjee and A. Ghosal, “Design and Analysis of a Low Power High-Performance GDI based Radix 4 Multiplier Using Modified Booth Wallace Algorithm,” in 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018, pp. 247-251, doi: 10.1109/EDKCON.2018.8770494.
[16] R. Zendegani, M. Kamal, M. Bahadori, A. Afzali-Kusha, and M. Pedram, “RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, pp. 393-401, 2017, doi: 10.1109/TVLSI.2016.2587696.
[17] Y. Luo, Y. Wang, H. Sun, Y. Zha, Z. Wang, and H. Pan, “CORDIC-Based Architecture for Computing Nth Root and Its Implementation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 4183-4195, 2018, doi: 10.1109/TCSI.2018.2835822.
[18] A. Mokhtar, S. A. Karim, S. P. Chew, S. M. F. S. M. Dardin, L. S. Supian, and F. Hashim, “FPGA implementation of CORDIC algorithm in digital modulation,” Journal of Fundamental and Applied Sciences, vol. 9, pp. 279, 2018, doi: 10.4314/jfas.v9i3s.23.
[19] M. Heidarpur et al., “CORDIC-SNN: On-FPGA STDP Learning With Izhikevich Neurons,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2235-2245, 2019, doi: 10.1109/TCSI.2019.2899356.
[20] A. Boettcher and M. Kumm, “Towards Globally Optimal Design of Multipliers for FPGAs,” IEEE Transactions on Computers, pp. 1–13, Jan. 2023, doi: 10.1109/TC.2023.3238128.
[21] D. Perišić, “NEW KIND OF IIR DIGITAL FILTERS INTENDED FOR PULSE PERIOD FILTERING,” Revue Roumaine des Sciences Techniques, Série Électrotechnique et Énergétique, vol. 69, pp. 61-66, 2024, doi: 10.59277/RRST-EE.2024.1.11.
[22] S. Raveendran, P. Edavoor, N. Balachandra, and M. Vasantha, “Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic,” IEEE Access, vol. 9, pp. 108119-108130, 2021, doi: 10.1109/ACCESS.2021.3100892.
[23] M. H. Haider and S.-B. Ko, “Booth Encoding-Based Energy Efficient Multipliers for Deep Learning Systems,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 6, pp. 2241-2245, June 2023, doi: 10.1109/TCSII.2022.3233923.
[24] B. V. Dharani et al., “Booth Multiplier: The Systematic Study,” in ICCCE 2020, Springer, Singapore, 2021, pp. 28-33, doi: 10.1007/978-981-15-7961-5_88.
[25] B. Mahesh and T. Srivasarao, “Performance Evaluation of FFT through Adaptive Hold Logic (AHL) Booth Multiplier,” in 2023 International Conference for Advancement in Technology (ICONAT), 2023, pp. 1-6, doi: 10.1109/ICONAT57137.2023.10080290.
[26] P. Singh and M. Kumar, “Design of Partial Product Generator Circuit for Approximate Radix-8 Booth Multiplier with Lower Delay,” in VLSI, Microwave and Wireless Technologies, Springer, Singapore, 2023, pp. 1-1, doi: 10.1007/978-981-19-0312-0_53.
[27] K. Rayudu, D. Jahagirdar, and P. Rao, “Design and testing of systolic array multiplier using fault injecting schemes,” Computer Science and Information Technologies, vol. 3, no. 1, pp. 1-9, 2022, doi: 10.11591/csit.v3i1.p1-9.
[28] V. Pala, V. Makhe, K. Bhuva, and R. Parekh, “RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier,” in 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO), 2022, pp. 1-6, doi: 10.1109/5nano53044.2022.9828876.
[29] V. Sm and K. Suresh, “An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform,” International Journal of Electrical and Computer Engineering (IJECE), vol. 9, no. 4, pp. 2433-2442, 2019, doi: 10.11591/ijece.v9i4.pp2433-2442.
[30] R. Gayathri et al., “VLSI Design of Approximate Baugh-Wooley Multiplier for Image Edge Computing,” Naksh Solutions, International Journal of Advanced Research in Science, Communication and Technology, ISSN: 2581-9429, 2023, doi: 10.48175/IJARSCT-9537.
[31] A. Sadeghi, N. Shiri, M. Rafiee, and M. Tahghigh, “An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending,” Frontiers of Information Technology & Electronic Engineering, vol. 23, pp. 950 - 965, 2022, doi: 10.1631/FITEE.2100432.
[32] F. A. Escobar Revelo, V. H. Mosquera Leyton, and C. F. Rengifo Rodas, “Tomografía de impedancia eléctrica: fundamentos de hardware y aplicaciones médicas,” Ing. Solidar., vol. 16, no. 3, Sep. 2020, doi: 10.16925/2357-6014.2020.03.02.
[33] M. Saha and A. Dandapat, “Modified Baugh Wooley Multiplier using Low Power Compressors,” in 2021 2nd International Conference for Emerging Technology (INCET), 2021, pp. 1-6, doi: 10.1109/INCET51464.2021.9456141.
[34] B. Zhang, Z. Cheng, and M. Pedram, “A High-Performance Low-Power Barrett Modular Multiplier for Cryptosystems,” in 2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2021, pp. 1-6, doi: 10.1109/ISLPED52811.2021.9502490.
[35] B. Jeevan, P. Samskruthi, P. Sahithi, and K. Sivani, “Implementation of parallel multiplier based on Booth computing method using FPGA,” in 2022 International Conference on Advances in Computing, Communication and Applied Informatics (ACCAI), 2022, pp. 1-8, doi: 10.1109/ACCAI53970.2022.9752479.
[36] P. Karuppusamy, “Design and Analysis of Low-Power, High-Speed Baugh Wooley Multiplier,” Journal of Electronic Imaging, 2019, pp. 60-70, doi: 10.36548/jei.




